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Low Power Interconnect Design 2012 edition
Sandeep Saini
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Low Power Interconnect Design 2012 edition
Sandeep Saini
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.
200 pages, 75 black & white illustrations
| Media | Books Hardcover Book (Book with hard spine and cover) |
| Released | June 15, 2015 |
| ISBN13 | 9781461413226 |
| Publishers | Springer-Verlag New York Inc. |
| Pages | 152 |
| Dimensions | 163 × 246 × 14 mm · 417 g |
| Language | English |
